1. Field of the Invention
The present invention relates to the electronic design of integrated circuits, and more specifically to a method and apparatus for the functional verification of a target integrated circuit design.
2. Related Art
Functional verification is one of the steps in the design of many integrated circuits. Functional verification generally refers to determining whether a design (xe2x80x9ctarget designxe2x80x9d) representing an integrated circuit performs a function it is designed for. In a typical design process, a designer identifies the functions to be performed and designs a circuit using high-level languages (e.g., VHDL language well known in the relevant arts) to perform the identified functions. An example of a function may be to generate a predetermined output data corresponding to a given input data. Tools available in the industry are typically used to generate a lower-level design (e.g., at gate-level) from the design specified in a high-level language. The higher level languages are generally more understandable to a user (human-being) while the lower level languages are closer in representation to the physical implementation.
Usually, the lower level design is evaluated against input data to generate output data. A determination of the accuracy of a functional design may be made based on the output data. The manner in which input data is generated and output data is used for determination of accuracy may depend on the specific type of verification environment. For example, in an emulation environment, the target design receives input data in a xe2x80x9creal environmentxe2x80x9d usually having other components, whose operation can be relied on for accuracy. The target design is implemented to typically operate at least with these other components. By testing the target design in combination with these other components, functional verification of the target design can be performed. In general, a functional verification system operating in an emulation environment needs to generate output data values quickly such that the output data is available in a timely manner for the other components.
In contrast, in a simulation environment, a designer specifies pre-determined input data and evaluates the target design against the input data. The output data generated by the evaluation is examined to determine whether the design performs the desired functions. Once a designer is satisfied with a design, the data representing the design is sent for fabrication as an integrated circuit.
Accuracy in the functional verification is an important requirement in the design process for several reasons. For example, it is relatively less expensive to alter a circuit design prior to fabrication compared to re-designing and sending the design data for fabrication. In addition, it may require several weeks of time to redesign and complete fabrication again. Such levels of delays may be unacceptable, particularly in the high-technology markets where short design cycles are generally important.
In addition to accuracy, the verification step needs to scale well to the functional verification of integrated circuits of large sizes. That is, a verification systems needs to provide for verification of integrated circuit designs of large sizes. As is well known, an integrated circuit (semi-conductor chip) can include transistors of the order of a few millions, and the number has been increasing over time.
Furthermore, it is generally desirable that the verification step be completed quickly or with minimal internal computations. The speed of verification is particularly important in view of the increase in size and complexity of integrated circuits. To decrease the total design cycle time, it is desirable that the functional verification be completed quickly.
Co-pending U.S. Patent Application entitled, xe2x80x9cFunctional Verification of Integrated Circuit Designsxe2x80x9d, Ser. No. 09/097,874, Filed: Jun. 15, 1998, describes some functional verification systems in which a target design is partitioned into many combinatorial logic blocks connected by sequential elements (e.g., flip-flops) and with appropriate dependencies. The state tables corresponding to the logic blocks are evaluated and stored in multiple random access storage devices (RASDs).
The output corresponding to each input combination is stored such that the output is retrieved from the corresponding RASD when the input combination is provided as a memory address to the RASD. For example, assuming a four input combinatorial logic and a RASD having four bits address bus, if the output the combinatorial logic is to be a 1 corresponding to an input of 1011, a xe2x80x981xe2x80x99 is stored in the memory location corresponding to address 1011.
Cross-connects (XCONs) may interconnect the RASDs and enforce the dependencies which preserve the overall function of the target design. In general, the XCONs provide the outputs resulting from evaluation as memory addresses to RASDs. An XCON may be connected to multiple RASDs, and the XCON together with the connected RASDs may be referred to as a combinatorial logic output evaluator (CLOE).
In an approach described in the co-pending application noted above, each CLOE is connected to 16 other CLOEs (termed as neighbors). One of these CLOEs acts as a central CLOE to communicate with other groups of 16 CLOEs. In other words, if the output of a combinatorial logic evaluated in a first group and the output is to be provided as an input to a RASD in another group, the central CLOEs of the two groups may need to communicate to enable the necessary data transfer.
Such an approach may have several disadvantages. For example, the scheduling of evaluation of a combinatorial block may be undesirably complicated as the inputs may need to be communicated from several CLOEs and due to the xe2x80x98hierarchyxe2x80x99 in communication resulting from the central CLOE. Accordingly, the embodiments of the co-pending application may not be suitable in some environments.
Therefore, what is needed is a method and apparatus which enables the CLOE outputs to be communicated in an efficient manner such that the evaluations can be scheduled and performed quickly. In addition, the approach generally needs to allows for one or more of several related features such as tracing, verification of cycle based and non-cycle based designs, etc.
A run time controller controls the sequence in which the combinatorial blocks forming a target design are evaluated. Multiple combinatorial blocks are grouped into a cluster, which is identified by a cluster number. Evaluation units are designed to evaluate the combinatorial blocks within a cluster in parallel. The run time controller sends a cluster number to the evaluation units to cause each evaluation unit to evaluate any assigned combinatorial blocks falling within the corresponding cluster. The run time controller may send a sequence of cluster numbers to cause the clusters to be evaluated in a desired sequence consistent with the dependencies present in the target design.
In an embodiment, the run time controller contains a data unit, a flow processor, flow control memory and a cluster control memory. Usually, the data unit receives one or more evaluation outputs from a evaluation unit and sends the received outputs to many evaluation units on a bus such that the evaluation outputs are available to the many evaluation units for any subsequent evaluations. However, the data unit may be designed to inject data from different sources onto the bus and provide the data received on the bus to the sources such that different features may be provided in accordance with the present invention.
The flow control memory may be programmed with instructions which identify the sequence in which clusters are to be evaluated under different conditions. The cluster control memory may be programmed to specify the manner in which different condition registers are to be manipulated. In addition, the contents of the cluster control memory may specify when the data from different sources is to be injected onto the bus and when the data received on the bus is to be provided to the different sources.
The flow processor operates according to the instructions stored in flow control memory and cluster control memory. When the contents of the cluster control memory specify that data is to be retrieved from a source (e.g., primary input memory, simulation memory, or messaging unit) for injection onto the bus, the corresponding data is retrieved and stored in a bus. An instruction in the cluster control memory may then specify the exact time when the data in the injection register is to be injected onto the bus.
The transaction may serve as a basis for accessing data from a simulation memory, a messaging unit or a primary input memory available to evaluation units. In the case of simulation memory, the access address may also be provided during a prior evaluation cycle. Thus, a simulation memory read may be provided in accordance with the present invention.
A write operation may also be performed similarly into the simulation memory or to messaging unit. The content of the cluster control memory may specify when (the evaluation outputs of which cluster) the data received from the evaluation units is to be provided to simulation memory or messaging unit, and the evaluation outputs are provided accordingly. In the case of simulation memory write, the address for writing the data may be formed from the evaluation outputs.
A non-cycle based design may also be verified using the run time controller provided in accordance with the present invention. The ability to modify the condition registers and counters can be used to implement the evaluation of loops until a desired condition is attained, which forms the basis for evaluating non-cycle based designs.
Thus, a run time controller provided in accordance with the present invention provides the ability to control the sequence of evaluations as the run time controller can send the cluster numbers to cause the evaluation units to evaluate the corresponding cluster.
A run time controller may provide the ability to simulate a memory as the present invention provides the ability to read and write at memory locations having addresses generated by prior evaluations.
A run time controller in accordance with the present invention may also allow data to be transferred between evaluation units and an external system as the data can be sent to and received from a messaging unit,
A run time controller in accordance with the present invention may further allow verification of non-cycle based designs as loops may be evaluated until a desired condition is attained.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.